I'm a recent electronics undergraduate student from VJTI, Mumbai and I do have a great interest in Digital VLSI, FPGA prototyping, RTL Design, and verification. In my undergrad, I tinkered a lot with FPGAs, Microcontrollers, and circuit designs. I have made my small RISC-V core in Verilog. Also made a 8 bit computer using SAP (Simple as possible!) Logic and simulated it in Logisim.
Right now I'm working in AMD, Bangalore as a Silicon Design Engineer. I'm responsible for SOC Level verification of Debug Unit related IPs.
Last summer, I worked with LAP (processor architecture Laboratory) under guidance of Prof.Paolo Ienne as a summer EPFL research student. I had worked on extending dynamtic (a dynamic HLS) support for External memory via AXI Interconnect, handling variable delay via accessing memory in a dynamic environment was amazing learning.
I'm a former verification Research Intern at SHAKTI, RISE LAB, IITM. SHAKTI is an open-source initiative by RISE group at IIT-Madras with the aim to produce production grade SOCs. I worked on accelerating the Verification flow of SHAKTI processors using FPGAs.
I was also selected in Google Summer of Code 2021 (GSOC'21) with beagleboard org. I had worked on an FPGA cape named BeagleWire and developed Gateware for it. I'm always open to Research opportunities in Computer Architecture, RTL Design, Verification, and FPGA prototyping.

Check my resume for more details: [CV]
Contact me on oabhilare_b19@el.vjti.ac.in

Education

Veermata Jijabai Technological Institute, Mumbai, India.
B.Tech in Electronics Engineering (CGPA: 9.13/10) (2018-2022)

• Relavant Coursework : Electronics Circuit Analysis and Design, Digital Combinational Circuits, Digital Sequential Circuits, Microprocessor and Microcontroller, Principle of VLSI, Embedded Systems
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Skills

• FPGAs : Xilinx’s Arty A7-100, KV260, Zynq ZC702, Altera’s Cyclone II, Lattice’s ICE40UP5K & iCE40HX4k, Anlogic’s EG4S20
• Langugaes : Verilog, VHDL, C, Python, Assembly Language(x86, RISC-V).
• EDA Tools : Quartus Prime, Xilinx Vivado, IceStorm.
• Microcontrollers : ESP32, ESP8266, Atmega328p, AM335x.
• Software & Frameworks : CoCotb, Icarus Verilog, GTKWave, Autodesk Eagle, Altium, Kicad, Proteus, Multisim, Logisim, Git, Linux.

Gist About Me

• I’m currently working in AMD as a silicon design engineer in the DFD Verification team. I’m responsible for SOC Level verification of Debug unit-related IPs of various AMD processors.
• Last summer, I worked with the Prof. Paolo Ienne of the Processor Architecture lab(lap), EPFL as a research intern. My research project with LAP, included adding support for external memory access in dynamatic (A dynamic HLS compiler). I worked with developing a custom AXI master, interfacing it with dynamic Load Store Queues of dynamatic and handling variable delays from memory.
• Before that, I had worked with AMD, India as a digital design verification co-op intern. I developed various SOC Level verification test cases for AMD processors.
• Last summer, I had done a project in google summer of code, 21 with beagleboard organization where I developed gateware for a Lattice FPGA cape. The gateware included interfacing FPGA and TI microprocessor. It also included bringing up FPGA with an SDRAM controller for SDRAM access.
• I’m a former verification Research Intern at SHAKTI, RISE LAB, IITM. I was in their verification team and developed a framework to verify SHAKTI processors on FPGA. Verified SHAKTI processors on ARTY-A7 FPGA.
• In my undergrad thesis, I worked on Accelerating Deepfake Detection on AMD-Xilinx’s VCK5000 a versal architecture FPGA board. Worked done in this project won third prize in AMD-Xilinx’s Adaptive Computing Challenge. It was also accepted in Parallel and Distributed Computing, Applications and Technologies (PDCAT’22)
• In my undergrad, I tinkered a lot with FPGAs, Digital Designs. I have made my small RISC-V core and also a small 8-bit computer. My other projects can be found on my portfolio site.

Career Outline

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